This invention relates to a 40/80-core cable discriminating method of discriminating an IDE-bus-cable (an 80-core cable) having eighty core-wires or an IDE-bus-cable (a 40-core cable) having forty core-wires. The 80-core cable is required when a data transmitting speed not less than 66 MB/S should be achieved on an ultra DMA (ultra Direct Memory Access) system related to an IDE (Integrated Drive Electronics) bus which is standardized by ATA (AT Attachment)-standards (which will be called an “ATA (IDE) bus”).
As an interface between a personal computer and a peripheral storage apparatus, the ATA (IDE) bus developed by IBM (International Business Machines) corporation is known. The ATA (IDE) bus was designed at first as a data transmitting system performed by a CPU which uses a PIO system having 3.3 MB/S in clock speed by using the 40-core cable having eighteen inches (one and a half feet) in length. As the personal computer and the peripheral storage apparatus are accelerated in processing speed or data transmitting speed, the ATA (IDE) bus in the data transmitting system became a bus-bottleneck which obstructs an acceleration of the processing speed for the personal computer because the transmitting speed of 3.3 MB/S is too slow, Therefore the acceleration in speed of the ATA (IDE) bus is required. In order to meet the requirement, the ATA (IDE) bus of 3.3 MB/S has been settled into a MODE 0 as the basis of a compatible mode and a MODE 1 (5.2 MB/S), a MODE 2 (8.3 MB/S), a MODE 3 (11.1 MB/S), and a MODE 4 (16.7 MB/S) have been designed with accelerated transmitting speed and with compatibility to a lower level, each data transmitting speed being accelerated by only shortening intervals of transmitted data. On the other hand, the ATA (IDE) bus using a DMA (Direct memory Access) system and which does not utilize the PIO system for data transmission was designed. Because the DMA system does not use the CPU for data transmission, the DMA system has a merit such that a load of the CPU can be reduced. As the DMA system, a MODE 0 (4 MB/S), a MODE 1 (13.3 MB/S), and a MODE 2 (16.7 MB/S) have been designed.
With the data transmitting speed of 16.6 MB/S or 16.7 MB/S as the fastest speed by the PIO and the DMA systems, however, it became the bus bottleneck because the processing speeds of the personal computer and the peripheral apparatus were further accelerated recently and therefore more acceleration of the data transmitting speed of the ATA (IDE) bus was required. However, the acceleration of the data transmitting speed by only shortening the intervals of the transmitted data for further acceleration of the data transmission speed reached the margin as the intervals are excessively shortened and therefore sequent data interfere with each other. Therefore, the ultra DMA system was designed after the PIO and the DMA system. The ultra DMA system can, differently from the PIO and the DMA systems, provide correctness of data by specially giving a CRC (Cyclic Redundancy Check) data, that is, a data for detecting consistency after each burst transmission. The CRC data have a function as same as a parity data such as to check transmitted data include error or not. This thus provides further acceleration of the data transmitting speed so that the data transmitting speeds of 3.3 MB/S, 66.7 MB/S, and 100 MB/S are achieved.
However, when the 40-core cable having eighteen inches is used for performing the data transmitting speed not less than 66 MB/S, it is difficult to provide the consistency of data because crosstalks occurs between each data transmitted in core wires. Therefore, it is difficult to realize the data transmitting speed not less than 66 MB/S. Thus, the 80-core cable has been designed in order to settle the matter.
It necessary for transmitting of the data transmitting speed not less than 66 MB/S without spoiling the signal quality to discriminate which the 80-core cable or the 40-core cable is used.
Related to a 40/80-core cable discriminating method, there is a discriminating method with using a PDIAG-signal included signals used in the ATA (IDE) bus. Although, the PDIAG-signal is originally used so that the personal computer can discriminate which a master storage apparatus or the master and a slave storage apparatuses is connected to the personal computer. Because the slave (and the master) storage apparatus(es) is (are) connected to the personal computer, the slave storage apparatus outputs the PDIAG-signal in a LOW state. Namely, the PDIAG-signal is basically output as an “active=LOW” state from the slave storage apparatus. Consequently, the personal computer can discriminate that only the master storage apparatus is connected to the personal computer when a HIGH state is detected while that the master and the slave storage apparatuses are connected to the personal computer when the LOW state is detected.
Because the PDIAG-signal is basically used only when (a medium of) the slave storage apparatus is formatted, the PDIAG-signal is thus used for the 40/80-core cable discriminating method.
According to the wiring of the core wire of the PDIAG-signal mentioned above, the 40/80-core cable discriminating method can be performed for example as first and second methods as follows. In a first 40/80-core cable discriminating method, a capacitor is provided in the personal computer. On the other hand, in a second 40/80-core cable discriminating method, the PDIAG-signal is observed by a general-purpose IO (Input and Output) port.
The first method discriminates which the 80-core cable or the 40-core cable is use by using a recharging time for charging the capacitor. Because the PDIAG-signal is cut or broken off before the connector connected to the personal computer when the 80-core cable is connected to the personal computer, the PDIAG-signal is not connected to the capacitor. On the other hand, when the 40-core cable is connected to the personal computer, the PDIAG-signal is connected to the capacitor. Consequently, when the peripheral storage apparatus is ordered as “perform to discriminate the cable”, the peripheral storage apparatus sets the PDIAG-signal into a LOW state, switches into a TRI state, and switches into a HIGH state through a pull-up resistor of the peripheral storage apparatus. Namely, because each time for changing from the TRI state into the HIGH state is different from each other according as the peripheral storage apparatus is connected or disconnected to the capacitor, which the 80-core cable or the 40-core cable is used can be discriminated according to the difference of the changing time.
On the other hand, the second method has the personal computer capable of observing the PDIAG-signal. Because the PDIAG-signal is broken off before the connector connected to the personal computer while connected to the ground when the 80-core cable is used, the personal computer detects the LOW state. When the 40-core cable is used, the personal computer intactly detects the PDIAG-signal as the HIGH state. Thus, the personal computer discriminates as the 80-core cable when the LOW state is detected while as the 40-core cable when the HIGH state is detected.
The standards of the ATA (IDE) bus prescribe so that the master and the slave storage apparatuses can be at the same time connected to the personal computer as the peripheral storage apparatus. When the slave storage apparatus is connected to the personal computer, the PDIAG-signal provided from the slave storage apparatus may be in the LOW state depending on the situation. In this situations the personal computer may always detect the PDIAG-signal in the LOW state if each of the 40-core and the 80-core cables is connected to the personal computer. Therefore. the personal computer cannot discriminate which the 40-core or the 80-core cable is used.